This 128-bit quadruple precision is designed for applications needing results in higher than double precision,[1] and as a primary function, to allow computing double precision results more reliably and accurately by minimising overflow and round-off errors in intermediate calculations and scratch variables. William Kahan, primary architect of the original IEEE 754 floating-point standard noted, "For now the 10-byte Extended format is a tolerable compromise between the value of extra-precise arithmetic and the price of implementing it to run fast; very soon two more bytes of precision will become tolerable, and ultimately a 16-byte format ... That kind of gradual evolution towards wider precision was already in view when IEEE Standard 754 for Floating-Point Arithmetic was framed."[2]
In IEEE 754-2008 the 128-bit base-2 format is officially referred to as binary128.
The sign bit determines the sign of the number (including when this number is zero, which is signed). "1" stands for negative.
This gives from 33 to 36 significant decimal digits precision. If a decimal string with at most 33 significant digits is converted to the IEEE 754 quadruple-precision format, giving a normal number, and then converted back to a decimal string with the same number of digits, the final result should match the original string. If an IEEE 754 quadruple-precision number is converted to a decimal string with at least 36 significant digits, and then converted back to quadruple-precision representation, the final result must match the original number.[3]
The format is written with an implicit lead bit with value 1 unless the exponent is stored with all zeros (used to encode subnormal numbers and zeros). Thus only 112 bits of the significand appear in the memory format, but the total precision is 113 bits (approximately 34 decimal digits: log10(2113) ≈ 34.016) for normal values; subnormals have gracefully degrading precision down to 1 bit for the smallest non-zero value. The bits are laid out as:
Exponent encoding
The quadruple-precision binary floating-point exponent is encoded using an offset binary representation, with the zero offset being 16383; this is also known as exponent bias in the IEEE 754 standard.
Thus, as defined by the offset binary representation, in order to get the true exponent, the offset of 16383 has to be subtracted from the stored exponent.
The stored exponents 000016 and 7FFF16 are interpreted specially.
The minimum strictly positive (subnormal) value is 2−16494 ≈ 10−4965 and has a precision of only one bit. The minimum positive normal value is 2−16382 ≈ 3.3621 × 10−4932 and has a precision of 113 bits, i.e. ±2−16494 as well. The maximum representable value is 216384 − 216271 ≈ 1.1897 × 104932.
Quadruple precision examples
These examples are given in bit representation, in hexadecimal, of the floating-point value. This includes the sign, (biased) exponent, and significand.
4008 74d9 9564 5aa0 0c11 d0cc 9770 5e5b16 ≈ 745.69987158227021999999999999999997147 (closest approximation to the number of Watts corresponding to 1 horsepower)
By default, 1/3 rounds down like double precision, because of the odd number of bits in the significand. Thus, the bits beyond the rounding point are 0101... which is less than 1/2 of a unit in the last place.
Double-double arithmetic
A common software technique to implement nearly quadruple precision using pairs of double-precision values is sometimes called double-double arithmetic.[4][5][6] Using pairs of IEEE double-precision values with 53-bit significands, double-double arithmetic provides operations on numbers with significands of at least[4]2 × 53 = 106 bits (actually 107 bits[7] except for some of the largest values, due to the limited exponent range), only slightly less precise than the 113-bit significand of IEEE binary128 quadruple precision. The range of a double-double remains essentially the same as the double-precision format because the exponent has still 11 bits,[4] significantly lower than the 15-bit exponent of IEEE quadruple precision (a range of 1.8 × 10308 for double-double versus 1.2 × 104932 for binary128).
In particular, a double-double/quadruple-precision value q in the double-double technique is represented implicitly as a sum q = x + y of two double-precision values x and y, each of which supplies half of q's significand.[5] That is, the pair (x, y) is stored in place of q, and operations on q values (+, −, ×, ...) are transformed into equivalent (but more complicated) operations on the x and y values. Thus, arithmetic in this technique reduces to a sequence of double-precision operations; since double-precision arithmetic is commonly implemented in hardware, double-double arithmetic is typically substantially faster than more general arbitrary-precision arithmetic techniques.[4][5]
Note that double-double arithmetic has the following special characteristics:[8]
As the magnitude of the value decreases, the amount of extra precision also decreases. Therefore, the smallest number in the normalized range is narrower than double precision. The smallest number with full precision is 1000...02 (106 zeros) × 2−1074, or 1.000...02 (106 zeros) × 2−968. Numbers whose magnitude is smaller than 2−1021 will not have additional precision compared with double precision.
The actual number of bits of precision can vary. In general, the magnitude of the low-order part of the number is no greater than a half ULP of the high-order part. If the low-order part is less than half ULP of the high-order part, significant bits (either all 0s or all 1s) are implied between the significand of the high-order and low-order numbers. Certain algorithms that rely on having a fixed number of bits in the significand can fail when using 128-bit long double numbers.
Because of the reason above, it is possible to represent values like 1 + 2−1074, which is the smallest representable number greater than 1.
In addition to the double-double arithmetic, it is also possible to generate triple-double or quad-double arithmetic if higher precision is required without any higher precision floating-point library. They are represented as a sum of three (or four) double-precision values respectively. They can represent operations with at least 159/161 and 212/215 bits respectively. A natural extension to an arbitrary number of terms (though limited by the exponent range) is called floating-point expansions.
A similar technique can be used to produce a double-quad arithmetic, which is represented as a sum of two quadruple-precision values. They can represent operations with at least 226 (or 227) bits.[9]
Implementations
Quadruple precision is often implemented in software by a variety of techniques (such as the double-double technique above, although that technique does not implement IEEE quadruple precision), since direct hardware support for quadruple precision is, as of 2016[update], less common (see "Hardware support" below). One can use general arbitrary-precision arithmetic libraries to obtain quadruple (or higher) precision, but specialized quadruple-precision implementations may achieve higher performance.
Computer-language support
A separate question is the extent to which quadruple-precision types are directly incorporated into computer programming languages.
Quadruple precision is specified in Fortran by the real(real128) (module iso_fortran_env from Fortran 2008 must be used, the constant real128 is equal to 16 on most processors), or as real(selected_real_kind(33, 4931)), or in a non-standard way as REAL*16. (Quadruple-precision REAL*16 is supported by the Intel Fortran Compiler[10] and by the GNU Fortran compiler[11] on x86, x86-64, and Itanium architectures, for example.)
For the C programming language, ISO/IEC TS 18661-3 (floating-point extensions for C, interchange and extended types) specifies _Float128 as the type implementing the IEEE 754 quadruple-precision format (binary128).[12] Alternatively, in C/C++ with a few systems and compilers, quadruple precision may be specified by the long double type, but this is not required by the language (which only requires long double to be at least as precise as double), nor is it common.
As of C++23, the C++ language defines a <stdfloat> header that contains fixed-width floating-point types. Implementations of these are optional, but if supported, std::float128_t corresponds to quadruple precision.
On x86 and x86-64, the most common C/C++ compilers implement long double as either 80-bit extended precision (e.g. the GNU C Compiler gcc[13] and the Intel C++ Compiler with a /Qlong‑double switch[14]) or simply as being synonymous with double precision (e.g. Microsoft Visual C++[15]), rather than as quadruple precision. The procedure call standard for the ARM 64-bit architecture (AArch64) specifies that long double corresponds to the IEEE 754 quadruple-precision format.[16] On a few other architectures, some C/C++ compilers implement long double as quadruple precision, e.g. gcc on PowerPC (as double-double[17][18][19]) and SPARC,[20] or the Sun Studio compilers on SPARC.[21] Even if long double is not quadruple precision, however, some C/C++ compilers provide a nonstandard quadruple-precision type as an extension. For example, gcc provides a quadruple-precision type called __float128 for x86, x86-64 and Itanium CPUs,[22] and on PowerPC as IEEE 128-bit floating-point using the -mfloat128-hardware or -mfloat128 options;[23] and some versions of Intel's C/C++ compiler for x86 and x86-64 supply a nonstandard quadruple-precision type called _Quad.[24]
Zig provides support for it with its f128 type.[25]
Google's work-in-progress language Carbon provides support for it with the type called f128.[26]
As of 2024, Rust is currently working on adding a new f128 type for IEEE quadruple-precision 128-bit floats.[27]
Libraries and toolboxes
The GCC quad-precision math library, libquadmath, provides __float128 and __complex128 operations.
The Boost multiprecision library Boost.Multiprecision provides unified cross-platform C++ interface for __float128 and _Quad types, and includes a custom implementation of the standard math library.[28]
The Multiprecision Computing Toolbox for MATLAB allows quadruple-precision computations in MATLAB. It includes basic arithmetic functionality as well as numerical methods, dense and sparse linear algebra.[29]
The DoubleFloats[30] package provides support for double-double computations for the Julia programming language.
The doubledouble.py[31] library enables double-double computations in Python. [citation needed]
Native support of IEEE 128-bit floats is defined in PA-RISC 1.0,[35] and in SPARC V8[36] and V9[37] architectures (e.g. there are 16 quad-precision registers %q0, %q4, ...), but no SPARC CPU implements quad-precision operations in hardware as of 2004[update].[38]
Non-IEEE extended-precision (128 bits of storage, 1 sign bit, 7 exponent bits, 112 fraction bits, 8 bits unused) was added to the IBM System/370 series (1970s–1980s) and was available on some System/360 models in the 1960s (System/360-85,[39] -195, and others by special request or simulated by OS software).
The Siemens 7.700 and 7.500 series mainframes and their successors support the same floating-point formats and instructions as the IBM System/360 and System/370.
The VAX processor implemented non-IEEE quadruple-precision floating point as its "H Floating-point" format. It had one sign bit, a 15-bit exponent and 112-fraction bits, however the layout in memory was significantly different from IEEE quadruple precision and the exponent bias also differed. Only a few of the earliest VAX processors implemented H Floating-point instructions in hardware, all the others emulated H Floating-point in software.
The NEC Vector Engine architecture supports adding, subtracting, multiplying and comparing 128-bit binary IEEE 754 quadruple-precision numbers.[40] Two neighboring 64-bit registers are used. Quadruple-precision arithmetic is not supported in the vector register.[41]
The RISC-V architecture specifies a "Q" (quad-precision) extension for 128-bit binary IEEE 754-2008 floating-point arithmetic.[42] The "L" extension (not yet certified) will specify 64-bit and 128-bit decimal floating point.[43]
Quadruple-precision (128-bit) hardware implementation should not be confused with "128-bit FPUs" that implement SIMD instructions, such as Streaming SIMD Extensions or AltiVec, which refers to 128-bit vectors of four 32-bit single-precision or two 64-bit double-precision values that are operated on simultaneously.
See also
IEEE 754, IEEE standard for floating-point arithmetic
^Schwarz, E. M.; Krygowski, C. A. (September 1999). "The S/390 G5 floating-point unit". IBM Journal of Research and Development. 43 (5/6): 707–721. CiteSeerX10.1.1.117.6711. doi:10.1147/rd.435.0707.
^Gerwig, G.; Wetter, H.; Schwarz, E. M.; Haess, J.; Krygowski, C. A.; Fleischer, B. M.; Kroener, M. (May 2004). "The IBM eServer z990 floating-point unit. IBM J. Res. Dev. 48". pp. 311–322.
^Weaver, David L.; Germond, Tom, eds. (1994). The SPARC Architecture Manual: Version 9 (archived copy on web.archive.org)(PDF). SPARC International, Inc. Archived from the original(PDF) on 2012-01-18. Retrieved 2011-09-24. Floating-point: The architecture provides an IEEE 754-compatible floating-point instruction set, operating on a separate register file that provides 32 single-precision (32-bit), 32 double-precision (64-bit), 16 quad-precision (128-bit) registers, or a mixture thereof.
^"SPARC Behavior and Implementation". Numerical Computation Guide — Sun Studio 10. Sun Microsystems, Inc. 2004. Retrieved 2011-09-24. There are four situations, however, when the hardware will not successfully complete a floating-point instruction: ... The instruction is not implemented by the hardware (such as ... quad-precision instructions on any SPARC FPU).
^Padegs, A. (1968). "Structural aspects of the System/360 Model 85, III: Extensions to floating-point architecture". IBM Systems Journal. 7: 22–29. doi:10.1147/sj.71.0022.
