MOSISMOSIS (Metal Oxide Semiconductor Implementation Service) is multi-project wafer service that provides metal–oxide–semiconductor (MOS) chip design tools and related services that enable universities, government agencies, research institutes and businesses to prototype chips efficiently and cost-effectively. Operated by the University of Southern California's Information Sciences Institute (ISI), MOSIS combines customers' orders onto shared multi-project wafers that speed production and reduce costs compared with underutilized single-project wafers. Customers are able to debug and adjust designs, or to commission small-volume runs, without making major production investments. Fabrication costs are also shared by combining multiple designs from a single customer onto one "mask set," or wafer template. According to MOSIS, by the end of 2016, the service had delivered more than 60,000 integrated circuit designs.[1] Funded by DARPA,[2] MOSIS was created in 1980[3] by ISI's Danny Cohen, an Internet pioneer who also developed Voice over Internet Protocol and Video over Internet Protocol.[4] It was based on the revolutionary VLSI design methodology of Carver Mead and Lynn Conway, who pioneered and/or popularized the use of technology-independent design rules and modular cell-based, hierarchical system design, testing this new approach to rapid prototyping and short-run fabrication at Xerox PARC.[5] One of the first e-commerce providers, MOSIS also launched the "fabless foundry" industry, in which vendors outsource chip fabrication rather than manufacturing them in-house.[6] Thousands of students also have learned chip design in MOSIS-associate programs.[7] Many early MOSIS users were students trying IC layout techniques from the seminal book Introduction to VLSI Design (ISBN 0-201-04358-0) published in 1980 by Caltech professor Carver Mead[8] and PARC researcher Lynn Conway, who taught the world's first VLSI class at MIT.[9][10] Some early reduced instruction set computing (RISC) processors such as MIPS (1984) and SPARC (1987) were run through MOSIS during their early design and testing phases. MOSIS in the 1980sAfter the transfer of Xerox PARC's multi-project wafer (MPW) technology to USC/ISI[3], the MOSIS Project was created, and the first trial run conducted in August 1980[11]:
The service became operational in January 1981, with 5-micron nMOS as the first fabrication technology offered; designs were submitted in Caltech Intermediate Form via the ARPANET.[11] By 1983, more than forty organizations were using the service.[12] Chips were returned to designers approximately a month after the close of a fabrication run. Over the course of the 1980s, more than 12,000 projects were fabricated through the MOSIS service.[13] After the initial 5-micron, 1-metal layer nMOS service, new technologies were introduced, advancing to 1.2-micron, 2-metal layer CMOS by 1988. At the end of the 1980s, gallium arsenide (GaAs) fabrication service was added.[14]
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